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2-Bus CPU Architecture (2-バス アーキテクチャ)

Example: the 2-bus add instruction



Step Actions
T0 MA $\leftarrow$ PC
T1 PC $\leftarrow$ PC + 4; MD $\leftarrow$ M[MA]
T2 IR $\leftarrow$ MD
T3 A $\leftarrow$ R[ra]
T4 R[rc] $\leftarrow$ A + R[rb]


  
Figure 2.2: Data flow for a 2-bus CPU architecture
\includegraphics[height=13cm]{/home/david/courses/comparch/lectures/cpu/figs/2bus.eps}



David Asano
2001-05-29