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3-Bus CPU Architecture (3-バス アーキテクチャ)

Example: the 3-bus add instruction

Step Actions
T0 MA $\leftarrow$ PC; MD $\leftarrow$ M[MA]; PC $\leftarrow$ PC + 4;
T1 IR $\leftarrow$ MD
T2 R[rc] $\leftarrow$ R[ra] + R[rb]

Figure 2.3: Data flow for a 3-bus CPU architecture

David Asano