next up previous contents
Next: Speeding up the System Up: Improving Performance (性能向上へ) Previous: 2-Bus CPU Architecture (2-バス

3-Bus CPU Architecture (3-バス アーキテクチャ)



Example: the 3-bus add instruction



Step Actions
T0 MA $\leftarrow$ PC; MD $\leftarrow$ M[MA]; PC $\leftarrow$ PC + 4;
T1 IR $\leftarrow$ MD
T2 R[rc] $\leftarrow$ R[ra] + R[rb]


  
Figure 2.3: Data flow for a 3-bus CPU architecture
\includegraphics[height=13cm]{/home/david/courses/comparch/lectures/cpu/figs/3bus.eps}



David Asano
2001-05-29