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Speeding up the System Clock (クロック周波数増大)


  
Figure 2.4: CPU data path timing
\includegraphics[width=11cm]{/home/david/courses/comparch/lectures/cpu/figs/timing.eps}



Example timing parameters



Name Parameter TTL Gates GaAs Gates
Gate propagation delay tg 5 ns 150 ps
(ゲート伝搬遅延)      
Bus propagation delay tbp 5 ns 500 ps
(assumed)      
Logic propagation delay tcomb 14 ns 400 ps
Latch propagation delay tl 6 ns 440 ps
Minimum clock period tmin 30 ns (33 MHz) 1490 ps (670 MHz)


next up previous contents
Next: Increasing the Data Width Up: Improving Performance (性能向上へ) Previous: 3-Bus CPU Architecture (3-バス
David Asano
2001-05-29