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RISC Architecture (RISC アーキテクチャ)

$\Rightarrow$ introduction of RISC architecture

Example: SPARC (Scalable Processor ARChictecture)

op=opcode, disp30=displacement, a=annul bit, cond=branch condition,

op2=opcode for format 2, disp22=displacement, rd=destination register,

op3=opcode for format 3, rs1=source register 1, opf=sub-opcode for

floating-point, rs2=source register 2, simm13=signed immediate operand


next up previous contents
Next: CPU Architecture (II) - Up: CPU Architecture (I) - Previous: CISC Architecture (CISC アーキテクチャ)
David Asano
2001-05-29