x_{3} |
x_{2} |
x_{1} |
x_{0} |
Multiplicand | ||||

y_{3} |
y_{2} |
y_{1} |
y_{0} |
Multiplier | ||||

(xy_{0})_{4} |
(xy_{0})_{3} |
(xy_{0})_{2} |
(xy_{0})_{1} |
(xy_{0})_{0} |
pp_{0} |
|||

(xy_{1})_{4} |
(xy_{1})_{3} |
(xy_{1})_{2} |
(xy_{1})_{1} |
(xy_{1})_{0} |
pp_{1} |
|||

(xy_{2})_{4} |
(xy_{2})_{3} |
(xy_{2})_{2} |
(xy_{2})_{1} |
(xy_{2})_{0} |
pp_{2} |
|||

(xy_{3})_{4} |
(xy_{3})_{3} |
(xy_{3})_{2} |
(xy_{3})_{1} |
(xy_{3})_{0} |
pp_{3} |
|||

p_{7} |
p_{6} |
p_{5} |
p_{4} |
p_{3} |
p_{2} |
p_{1} |
p_{0} |

*Unsigned array multiplier (3-bit)*

- each box is a 1-bit full adder:
*c*_{out}*p*_{out}=*xy*+*p*_{in}+*c*_{in} - an
*m*-bit multiplier requires*m*^{2}full adders - propagation delay is about 4
*m*gates

*Signed multiplication*

- in 2's complement representation, an
*m*-bit number has a value

- multiplication is the same as for unsigned numbers except that the last partial product is subtracted instead of added

*2's complement series parallel multiplier (4-bit)*

Operation (refer to Figure 4.2)

- 1.
- clear the accumulator
- 2.
- add the product of
xandy_{0}- 3.
- shift accumulator and
yregisters right by 1 bit- 4.
- repeat 2-3 if
y_{3}is not in the rightmost position- 5.
- subtract the product of
xandy_{3}

*Example
*

6 | 0 | 1 | 1 | 0 | |||||

1 | 0 | 1 | 1 | ||||||

pp_{0} (subtract=0) |
0 | 0 | 1 | 1 | 0 | ||||

add/shift (accum.) | 0 | 0 | 0 | 1 | 1 | 0 | |||

pp_{1} (subtract=0) |
0 | 0 | 1 | 1 | 0 | ||||

add/shift (accum.) | 0 | 0 | 1 | 0 | 0 | 1 | 0 | ||

pp_{2} (subtract=0) |
0 | 0 | 0 | 0 | 0 | ||||

add/shift (accum.) | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | |

pp_{3} (subtract=1) |
1 | 1 | 0 | 1 | 0 | ||||

add (accum.) | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |