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Hardware Structure (ハードウェア構造)

\includegraphics[width=8cm]{/home/david/courses/comparch/lectures/arith/figs/fpaddsub.eps}

1.
separate the sign, exponent and fraction fields
2.
shift the significand of the smaller number right by |e1 - e2| bits
3.
er = max(e1,e2)
4.
if add and s1=s2 or if subtract and $s_1\ne s_2$ then add the significands; else subtract them
5.
count the number of leading zeros z and shift the result significand right by z bits to normalize
6.
round the result significand
7.
adjust the result exponent by subtracting z and then bias
8.
combine the result sign, biased exponent and fraction bits



David Asano
2001-05-29