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Dynamic RAM Memory Cells (DRAM)



\includegraphics[width=8cm]{/home/david/courses/comparch/lectures/memory/figs/dramcell.eps}

DRAM Chip Architecture



$1M \times 1$ DRAM



\includegraphics[width=8cm]{/home/david/courses/comparch/lectures/memory/figs/1mx1dram.eps}

DRAM Read and Write Cycles



The timing for DRAM read and write cycles is shown in Figure 6.1.



Example: Intel 21040 $4M\times 1$ DRAM



tA=70ns, tC=130ns, tDHR=55ns,

maximum time between refreshes =16ms








  
Figure 6.1: DRAM timing for read and write cycles
\includegraphics[width=9.5cm]{/home/david/courses/comparch/lectures/memory/figs/dramtiming.eps}



DRAM Refresh



A typical DRAM refresh circuit is shown in Figure 6.2.


next up previous contents
Next: Comparison of SRAMs and Up: Random Access Memory (RAM) Previous: Static RAM Memory Cells
David Asano
2001-05-29